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publication# 18150 rev. a amendment /0 issue date: august 1993. www: 5/4/95 advanced micro devices am29030 and am29035 risc microprocessors with 8-kbyte/4-kbyte instruction cache preliminary ? ? am29030 microprocessor distinctive characteristics full 32-bit architecture 26 million instructions per second (mips) sustained at 33 mhz 8-kbyte, two-way set-associative instruction cache 33- and 25-mhz operating frequencies scalable clocking ? technology programmable 16- or 32-bit data bus width cmos technology/ttl-compatible 4-gbyte virtual address space with demand paging streamlined system interface for simplified, high-frequency operation burst-mode and page-mode access support 8-, 16-, or 32-bit rom interface 64-entry memory management unit on-chip fully pipelined on-chip timer facility 192 general-purpose registers three-address instruction architecture master/slave chip/output checking software compatible with am29005 ? and am29000 ? microprocessors advanced debugging support ieee std 1149.1-1990 (jtag) compliant standard test access port and boundary scan architecture implementation am29035 microprocessor distinctive characteristics the am29035 ? microprocessor is similar to the am29030 ? microprocessor except for the following differences: 4-kbyte, direct-mapped instruction cache 16-mhz operating frequency 12 million instructions per second (mips) sustained at 16 mhz simplified block diagram 32 32 or 16 instruction/data instruction/ data rom address instruction/ data ram instruction/data instruction/data address address 8, 16, or 32 32 or 16 32 or 16 am29030 and am29035 risc microprocessors with 8kbyte/4kbyte instruction cache
amd a d v a n c e i n f o r m a t i o n 2 am29030 and am29035 microprocessors table of contents distinctive characteristics 1 am29030 microprocessor 1 am29035 microprocessor 1 simplified block diagram 1 general description 3 29k family development support products 3 related amd products 3 third-party development support products 3 connection diagram 4 145-lead pga package 4 pga pin designations by pin number 5 pga pin designations by pin name 6 144-lead cerquad package 7 cerquad pin designations by pin number 8 cerquad pin designations by pin name 9 logic symbol 10 ordering information 11 absolute maximum ratings 12 operating ranges 12 dc characteristics over commercial operating ranges 12 capacitance 12 switching characteristics over commercial operating range 13 pga package 13 cerquad package 14 switching waveforms 15 capacitive output delays 16 switching test circuit 16 thermal characteristics 17 physical dimensions 18 gqd 144ecerquad trimmed and formed 18 cgy 145epin grid arraye**not currently available in this acrobat file** 19
amd p r e l i m i n a r y 3 am29030 and am29035 microprocessors general description the am29030 and am29035 risc microprocessors are high-performance, general-purpose, 32-bit micro- processors implemented in cmos technology. through high circuit densities and a high degree of on-chip integration, the am29030 and am29035 microproces- sors are capable of operating at high internal frequen- cies while providing the designer with a simple stream- lined external interface. the am29030 and am29035 microprocessors were designed to meet the common requirements of embedded applications such as laser beam printers, graphics processors, x terminals and servers, applica- tion program interface (api) accelerators, and scan- ners. the am29030 and am29035 microprocessors are well suited for these applications since they provide high performance at low cost, and offer the designer com- plete design flexibility. coupled with hardware and soft- ware development tools from amd ? and amd's fusion29k ? partners, no design is ever far from the marketplace. the am29030 microprocessor is available in a 145-lead pin-grid-array (pga) package and a 144-pin cerquad package. the pga has 111 signal pins, 26 power and ground pins, 7 reserved pins, and 1 alignment/ground pin. the cerquad has 111 signal pins, 30 power and ground pins, and 3 reserved pins. the am29035 microprocessor is available in a 144-pin cerquad package. 29k ? family development support products contact your local amd representative for information on the complete set of development support tools. software development products on several hosts: optimizing compilers for common high-level languages assembler and utility packages source- and assembly-level software debuggers target-resident development monitors simulators ez-030, an am29030 microprocessor-based evaluation board kit related amd products 29k family devices device description am29000 ? streamlined instruction microprocessor am29005 ? low-cost streamlined instruction microprocessor am29050 ? streamlined instruction microprocessor with on-chip floating point am29200 ? risc microcontroller am29205 ? low-cost risc microcontroller third-party development support products the fusion29k program of partnerships for application solutions provides the user with a vast array of products designed to meet critical time-to-market needs. products and solutions available through amd's fusion29k partners include: silicon products software generation and debug tools hardware development tools board level products laser printer solutions multiuser, kernel, and real-time operating systems graphics solutions networking and communications solutions manufacturing support custom support
amd p r e l i m i n a r y 4 am29030 and am29035 microprocessors connection diagram 145-lead pga bottom view abcdefghjklmnpq 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 note : pinout observed from pin side of package (pins facing viewer). pin number e-4 is defined for emulator access and is not a physical pin on the package (see the am29030 and am29035 microprocessors user's manual, order #15723, signal description section).
amd p r e l i m i n a r y 5 am29030 and am29035 microprocessors pga pin designations (sorted by pin number) pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 id4 c8 gnd h14 memclk n12 vcc a2 id0 c9 vcc h15 div2 n13 a1 a3 trst c10 gnd j1 id21 n14 erlya a4 tdi c11 vcc j2 id22 n15 err a5 tck c12 stat1 j3 gnd p1 id31 a6 test c13 wbc j13 inclk p2 a30 a7 i/d c14 hit j14 pwrclk p3 a27 a8 io/mem c15 intr 0 j15 breq p4 a24 a9 bwe 0 d1 id12 k1 id23 p5 a22 a10 bwe 2 d2 id11 k2 id24 p6 a20 a11 sup/us d3 id9 k3 vcc p7 a18 a12 opt0 d4 gnd k13 gnd p8 a15 a13 opt2 d13 di k14 req p9 a13 a14 mpgm1 d14 intr 1 k15 burst p10 a10 a15 stat2 d15 intr 2 l1 id25 p11 a8 b1 id7 e1 id14 l2 id26 p12 a6 b2 id6 e2 id13 l3 vcc p13 a4 b3 id3 e3 gnd l13 vcc p14 a2 b4 id1 e13 gnd l14 bgrt p15 a0 b5 tdo e14 intr 3 l15 pgmode q1 a31 b6 tms e15 trap 1 m1 id27 q2 a29 b7 r/w f1 id16 m2 id28 q3 a25 b8 warn f2 id15 m3 nc q4 a23 b9 bwe 1 f3 nc m13 gnd q5 a21 b10 bwe 3 f13 vcc m14 rdn q6 a19 b11 lock f14 reset m15 rdy q7 a17 b12 opt1 f15 trap 0 n1 id29 q8 a16 b13 mpgm0 g1 id18 n2 id30 q9 a14 b14 stat0 g2 id17 n3 nc q10 a12 b15 mserr g3 vcc n4 a28 q11 a11 c1 id10 g13 vcc n5 a26 q12 a9 c2 id8 g14 cntl0 n6 gnd q13 a7 c3 nc* g15 cntl1 n7 vcc q14 a5 c4 id5 h1 id20 n8 gnd q15 a3 c5 id2 h2 id19 n9 gnd c6 vcc h3 gnd n10 gnd c7 gnd h13 gnd n11 vcc notes: *1. nc = no connection internally. 2. pin number d4 is the alignment/ground pin and must be electrically connected to ground. 3. pin number e4 is defined for emulator access and is not a physical pin on the package (see am29030 and am29035 microprocessors user's manual, signal description section).
amd p r e l i m i n a r y 6 am29030 and am29035 microprocessors pga pin designation (sorted by pin name) pin no. pin name pin no. pin name pin no. pin name pin no. pin name p15 a0 b10 bwe 3 f1 id16 c12 stat1 n13 a1 g14 cntl0 g2 id17 a15 stat2 p14 a2 g15 cntl1 g1 id18 a11 sup/us q15 a3 h15 div2 h2 id19 a5 tck p13 a4 n14 erlya h1 id20 a4 tdi q14 a5 n15 err j1 id21 b5 tdo p12 a6 c7 gnd j2 id22 a6 test q13 a7 c8 gnd k1 id23 b6 tms p11 a8 c10 gnd k2 id24 f15 trap 0 q12 a9 d4 gnd l1 id25 e15 trap 1 p10 a10 e3 gnd l2 id26 a3 trst q11 a11 e13 gnd m1 id27 c6 vcc q10 a12 h3 gnd m2 id28 c9 vcc p9 a13 h13 gnd n1 id29 c11 vcc q9 a14 j3 gnd n2 id30 f13 vcc p8 a15 k13 gnd p1 id31 g3 vcc q8 a16 m13 gnd j13 inclk g13 vcc q7 a17 n6 gnd c15 intr 0 k3 vcc p7 a18 n8 gnd d14 intr 1 l3 vcc q6 a19 n9 gnd d15 intr 2 l13 vcc p6 a20 n10 gnd e14 intr 3 n7 vcc q5 a21 a7 i/d a8 io/mem n11 vcc p5 a22 a2 id0 b11 lock n12 vcc q4 a23 b4 id1 h14 memclk b8 warn p4 a24 c5 id2 b13 mpgm0 q3 a25 b3 id3 a14 mpgm1 n5 a26 a1 id4 b15 mserr p3 a27 c4 id5 a12 opt0 n4 a28 b2 id6 b12 opt1 q2 a29 b1 id7 a13 opt2 p2 a30 c2 id8 l15 pgmode q1 a31 d3 id9 j14 pwrclk l14 bgrt c1 id10 m14 rdn j15 breq d2 id11 m15 rdy k15 burst d1 id12 f14 reset reserved* a9 bwe 0 e2 id13 k14 req d13 di b9 bwe 1 e1 id14 b7 r/w c14 hit a10 bwe 2 f2 id15 b14 stat0 c13 wbc notes: *1. these following signals are reserved for future processor implementations. to maintain compatibility with future processor implementations, these pins should be connected to v cc by individual pull-up resistors. 2. pin number d4 is the alignment/ground pin and must be electrically connected to ground. 3. pin number e4 is defined for emulator access and is not a physical pin on the package (see am29030 andam29035 micropro- cessors user's manual, signal description section).
amd p r e l i m i n a r y 7 am29030 and am29035 microprocessors connection diagram 144-lead cerquad top view pin 1 pin 36 pin 73 pin 108 pin 109 pin 144 pin 37 pin 72
amd p r e l i m i n a r y 8 am29030 and am29035 microprocessors cerquad pin designations (sorted by pin number) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 v cc 37 v cc 73 v cc 109 a1 2 gnd 38 gnd 74 gnd 110 a0 3 mserr 39 id5 75 a29 111 erlya 4 stat2 40 id6 76 a28 112 err 5 stat1 41 id7 77 a27 113 rdn 6 stat0 42 id8 78 a26 114 rdy 7 mpgm1 43 id9 79 a25 115 bgrt 8 mpgm0 44 id10 80 a24 116 gnd 9 opt2 45 id11 81 a23 117 v cc 10 opt1 46 id12 82 a22 118 pgmode 11 opt0 47 id13 83 a21 119 burst 12 lock 48 id14 84 a20 120 req 13 sup/us 49 id15 85 a19 121 breq 14 bwe 3 50 v cc 86 a18 122 gnd 15 bwe 2 51 gnd 87 a17 123 inclk 16 bwe 1 52 id16 88 a16 124 v cc 17 bwe 0 53 id17 89 v cc 125 pwrclk 18 v cc 54 id18 90 gnd 126 memclk 19 gnd 55 id19 91 v cc 127 gnd 20 warn 56 id20 92 gnd 128 v cc 21 io/mem 57 id21 93 a15 129 gnd 22 i/d 58 id22 94 a14 130 div2 23 gnd 59 id23 95 a13 131 cntl0 24 v cc 60 gnd 96 a12 132 cntl1 25 r/w 61 v cc 97 a11 133 v cc 26 test 62 gnd 98 a10 134 gnd 27 tck 63 id24 99 a9 135 reset 28 tms 64 id25 100 a8 136 trap 0 29 tdi 65 id26 101 a7 137 trap 1 30 tdo 66 id27 102 a6 138 intr 3 31 trst 67 id28 103 a5 139 intr 2 32 id0 68 id29 104 a4 140 intr 1 33 id1 69 id30 105 a3 141 intr 0 34 id2 70 id31 106 a2 142 di 35 id3 71 a31 107 gnd 143 hit 36 id4 72 a30 108 v cc 144 wbc
amd p r e l i m i n a r y 9 am29030 and am29035 microprocessors cerquad pin designations (sorted by pin name) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 110 a0 16 bwe 1 45 id11 125 pwrclk 109 a1 15 bwe 2 46 id12 113 rdn 106 a2 14 bwe 3 47 id13 114 rdy 105 a3 131 cntl0 48 id14 135 reset 104 a4 132 cntl1 49 id15 120 req 103 a5 130 div2 52 id16 25 r/w 102 a6 111 erlya 53 id17 6 stat0 101 a7 112 err 54 id18 5 stat1 100 a8 2 gnd 55 id19 4 stat2 99 a9 19 gnd 56 id20 13 sup/us 98 a10 23 gnd 57 id21 27 tck 97 a11 38 gnd 58 id22 29 tdi 96 a12 51 gnd 59 id23 30 tdo 95 a13 60 gnd 63 id24 26 test 94 a14 62 gnd 64 id25 28 tms 93 a15 74 gnd 65 id26 136 trap 0 88 a16 90 gnd 66 id27 137 trap 1 87 a17 92 gnd 67 id28 31 trst 86 a18 107 gnd 68 id29 1 vcc 85 a19 116 gnd 69 id30 18 vcc 84 a20 122 gnd 70 id31 24 vcc 83 a21 127 gnd 123 inclk 37 vcc 82 a22 129 gnd 141 intr 0 50 vcc 81 a23 134 gnd 140 intr 1 61 vcc 80 a24 22 i/d 139 intr 2 73 vcc 79 a25 32 id0 138 intr 3 89 vcc 78 a26 33 id1 21 io/mem 91 vcc 77 a27 34 id2 12 lock 108 vcc 76 a28 35 id3 126 memclk 117 vcc 75 a29 36 id4 8 mpgm0 124 vcc 72 a30 39 id5 7 mpgm1 128 vcc 71 a31 40 id6 3 mserr 133 vcc 115 bgrt 41 id7 11 opt0 20 warn 121 breq 42 id8 10 opt1 119 burst 43 id9 9 opt2 17 bwe 0 44 id10 118 pgmode note: the following signals are reserved for future processor implementations: pin no. pin name 142 di 143 hit 144 wbc to maintain compatibility with future processor implementations, these pins should be connected to v cc by individual pull-up resistors.
amd p r e l i m i n a r y 10 am29030 and am29035 microprocessors logic symbol 4 2 2 r/w sup/us mpgm1mpgm0 bwe 3bwe 0 mserr opt2opt0 stat2stat0 pgmode io/mem a31a0 id31id0 memclk intr 3intr 0 cntl1cntl0 reset test inclk trap 1trap 0 2 4 3 3 32 pwrclk req trst tdo tms tdi tck i/d breq bgrt rdn erlya rdy err lock burst warn div2
amd p r e l i m i n a r y 11 am29030 and am29035 microprocessors ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am29030 20 c temperature range c = commercial (t c =0 c to +85 c) package type f = 144-lead cerquad (gqd144) g = 145-lead pin grid array without heat sink (cgy145) speed option device number/description am29030 risc microprocessor with 8 kbyte of instruction cache am29035 risc microprocessor with 4 kbyte of instruction cache valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations am2903033 gc am2903025 f am2903020 fc/w am2903516 33 = 33 mhz 25 = 25 mhz 20 = 20 mhz 16 = 16 mhz blank = for pga package only /w = for cerquad package only: denotes leads are trimmed/formed /w cerquad lead forming
amd p r e l i m i n a r y 12 am29030 and am29035 microprocessors absolute maximum ratings storage temperature 65 c to +150 c . . . . . . . . . . . . voltage on any pin with respect to gnd 0.5 to v cc +0.5 v . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices case temperature (t c )0 c to +85 c . . . . . . . . . . . . . . supply voltage (v cc ) +4.75 to +5.25 v . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges parameter pdii t c di i preliminary parameter symbol parameter description test conditions min max unit v il input low voltage 0.5 0.8 v v ih input high voltage 2.0 v cc +0.5 v v ilinclk inclk input low voltage 0.5 0.8 v v ihinclk inclk input high voltage 2.0 v cc +0.5 v v ilmemclk memclk input low voltage 0.5 0.8 v v ihmemclk memclk input high voltage v cc 0.8 v cc +0.5 v v ol output low voltage for all outputs except memclk i ol = 3.2 ma 0.45 v v oh output high voltage for all outputs except memclk i oh = 400 m a 2.4 v i li input leakage current 0.45 v v in v cc 0.45 v 10 m a i lo output leakage current 0.45 v v out v cc 0.4 v 10 m a i ccop operating power supply current v cc = 5.25 v, outputs floating; holding reset active with externally sup- plied memclk 16.7 mhz cerquad 20 mhz cerquad 25 mhz pga 33.3 mhz pga 30 30 28 27 ma/mhz v olc memclk output low voltage i olc = 20 ma 0.6 v v ohc memclk output high voltage i ohc = 20 ma v cc 0.6 v i osgnd memclk gnd short circuit current v cc = 5.0 v 100 ma i osvcc memclk v cc short circuit current v cc = 5.0 v 100 ma capacitance parameter pdii t c di i preliminary parameter symbol parameter description test conditions min max unit c in input capacitance 15 pf c inclk inclk input capacitance 20 pf c memclk memclk capacitance fc = 10 mhz 20 pf c out output capacitance 20 pf c i/o i/o pin capacitance 20 pf
amd p r e l i m i n a r y 13 am29030 and am29035 microprocessors switching characteristics over commercial operating range (pga) n p t preliminary ui n parameter test 25 mhz 33 mhz ui no. parameter description test conditions min max min max unit 1 inclk period (t) 40 100 30 100 ns 2 inclk high time 16 84 14.4 85.6 ns 3 inclk low time 16 84 14.4 85.6 ns 4 inclk rise time 0 6 0 6 ns 5 inclk fall time 0 6 0 6 ns 6 memclk delay from inclk notes 1, 2 0 6 0 6 ns 7 synchronous output valid delay for signals not broken out below memclk output memclk input 1 2 13 17 1 2 13 17 ns 7a synchronous output valid delay for id31id0 memclk output memclk input 1 2 13 17 1 2 13 17 ns 7b synchronous output valid delay for pgmode memclk output memclk input 1 2 13 19 1 2 13 19 ns 8 synchronous output invalid delay for signals not broken out below memclk output memclk input 1 2 13 17 1 2 13 17 ns 8a synchronous output invalid delay for id31id0 memclk output memclk input 1 2 13 17 1 2 13 17 ns 8b synchronous output invalid delay for pgmode memclk output memclk input 1 2 13 19 1 2 13 19 ns 9 synchronous input setup time for signals not broken out below (note 3) memclk output memclk input memclk = inclk 17 17 12 17 17 12 ns 9a synchronous input setup time for id31id0 (note 3) memclk output memclk input memclk = inclk 9 9 6 9 9 6 ns 9b synchronous input setup time for err (note 3) memclk output memclk input memclk = inclk 11 11 7 11 11 7 ns 9c synchronous input setup time for rdn (note 3) memclk output memclk input memclk = inclk 18 18 12 18 18 12 ns 10 synchronous input hold time memclk output memclk= inclk 0 2 0 2 ns 11 setup time for synchronous reset deassertion 2 2 ns 12 hold time for synchronous reset deassertion 5 5 ns 13 warn pulse width 4t 4t ns 14 asynchronous input pulse width t+10 t+10 ns 15 memclk high time memclk period=t memclk period=2t 16 t3 84 t+3 14.4 t3 85.6 t+3 ns 16 memclk low time memclk period=t memclk period=2t 16 t3 84 t+3 14.4 t3 85.6 t+3 ns 17 memclk rise time 0 5 0 5 ns 18 memclk fall time 0 5 0 5 ns notes: 1. memclk as an input is always cmos level. 2. memclk can drive an external load of 150 pf. 3. the input setup times with memclk used as an input are improved if memclk and inclk are tied to the same clock input. this is possible only if the processor and bus operate at the same frequency. 4. except where noted, measurement conditions are the same as the am29000 microprocessor. 5. all output valid delays are measured with v ol = 1.5 v and v oh = 1.5 v.
amd p r e l i m i n a r y 14 am29030 and am29035 microprocessors switching characteristics over commercial operating range (cerquad) n p t preliminary information ui n parameter test 16 mhz 20 mhz ui no. parameter description test conditions min max min max unit 1 inclk period (t) 60 100 50 100 ns 2 inclk high time 24 76 20 80 ns 3 inclk low time 24 76 20 80 ns 4 inclk rise time 0 6 0 6 ns 5 inclk fall time 0 6 0 6 ns 6 memclk delay from inclk notes 1, 2 0 6 0 6 ns 7 synchronous output valid delay for signal not broken out below memclk output memclk input 1 2 20 24 1 2 18 22 ns 7a synchronous output valid delay for id31id0 memclk output memclk input 1 2 22 26 1 2 20 24 ns 7b synchronous output valid delay for pgmode memclk output memclk input 1 2 22 26 1 2 20 24 ns 8 synchronous output invalid delay for signals not broken out below memclk output memclk input 1 2 20 24 1 2 18 22 ns 8a synchronous output invalid delay for id31id0 memclk output memclk input 1 2 22 26 1 2 20 24 ns 8b synchronous output invalid delay for pgmode memclk output memclk input 1 2 22 26 1 2 22 26 ns 9 synchronous input setup time for signals not broken out below (note 3) memclk output memclk input memclk = inclk 21 21 17 19 19 15 ns 9a synchronous input setup time for id31id0 (note 3) memclk output memclk input memclk = inclk 17 17 13 15 15 11 ns 9b synchronous input setup time for err (note 3) memclk output memclk input memclk = inclk 17 17 13 15 15 11 ns 9c synchronous input setup time for rdn (note 3) memclk output memclk input memclk = inclk 21 21 17 19 19 15 ns 10 synchronous input hold time memclk output memclk input 2 3 2 3 ns 11 setup time for synchronous reset deassertion 4 4 ns 12 hold time for synchronous reset deassertion 7 7 ns 13 warn pulse width 4t 4t ns 14 asynchronous input pulse width t+10 t+10 ns 15 memclk high time memclk period=t memclk period=2t 24 t3 76 t+3 20 t3 80 t+3 ns 16 memclk low time memclk period=t memclk period=2t 24 t3 76 t+3 20 t3 80 t+3 ns 17 memclk rise time 0 6 0 6 ns 18 memclk fall time 0 6 0 6 ns notes: 1. memclk as an input is always cmos level. 2. memclk can drive an external load of 150 pf. 3. the input setup times with memclk used as an input are improved if memclk and inclk are tied to the same clock input. this is possible only if the processor and bus operate at the same frequency. 4. except where noted, measurement conditions are the same as the am29000 microprocessor. 5. all output valid delays are measured with v ol = 1.5 v and v oh = 1.5 v.
amd p r e l i m i n a r y 15 am29030 and am29035 microprocessors switching waveforms inclk memclk 1 2 0.8 v 1.5 v 2.4 v 0.8 v 1.5 v v cc 1.0 v synchronous outputs synchronous inputs asynchronous inputs reset warn 5 16 18 15 7 7a 3 4 6 17 8 8a 10 9a 9 9b 11 12 13 14 7b 8b 9c
amd p r e l i m i n a r y 16 am29030 and am29035 microprocessors capacitive output delays for loads greater than 80 pf the following table describes the additional output delays for capacitive loads greater than 80 pf. values in the maximum additional delay column should be added to the value listed in the switching characteristics table. for loads less than or equal to 80 pf, refer to the delays listed in the switching characteristics table. this table applies to the pga package only. n ptditi preliminary no. parameter description total external capacitance (pf) maximum additional delay (ns) 7 synchronous memclk output valid delay 100 pf 150 pf 200 pf 250 pf 300 pf +1 ns +2 ns +4 ns +6 ns +8 ns 7a synchronous memclk output valid delay for id31id0 100 pf 150 pf 200 pf 250 pf 300 pf +1 ns +6 ns +10 ns +15 ns +19 ns switching test circuit am29030 or am29035 cpu v l i ol = 3.2 ma v ref = 1.5 v i oh = 400 m a c l v h note: c l is guaranteed to 80 pf. for capacitive loading greater than 80 pf, refer to the capacitive output delay table. pin under test v
amd p r e l i m i n a r y 17 am29030 and am29035 microprocessors thermal characteristics pin-grid-array package q ja q ca q jc thermal resistance c/watt q ja = q jc + q ca pin-grid-array package airflow (lfpm) 0 150 300 500 q jc junction-to-case 3 q ca case-to-ambient 20 18 16 13 cerquad package airflow (lfpm) 0 150 300 500 q jc junction-to-case 7.5 q ca case-to-ambient 20.8 18.7 16.4 13.3
amd p r e l i m i n a r y 18 am29030 and am29035 microprocessors physical dimensions 0.22 0.38 27.50 28.10 31.00 31.40 22.75 ref 27.50 28.10 31.00 31.40 22.75 ref 3.20 3.60 3.95 max 0.25 min top view side view 20000a ck 64 08/03/93 mh gqd 144 e cerquad trimmed and formed (metric unit) cap base see detail a 0.400 min 0.127 .05 r 0.305 .05 r 0 q 7 0.13 0.23 seal glass detail a 0.80 .10 5 2
amd p r e l i m i n a r y 19 am29030 and am29035 microprocessors cgy 145 pin grid array (pga) **this diagram is not currently available in this acrobat file. to order a printed document that contains this information, please call amd's facts-on-demand ? fax information service at 8002229323, or call the literature hotline at 5126025651 (direct dial worldwide) or 8002929263 (toll-free for u.s.)** trademarks amd, am29000 and fusion29k are registered trademarks; and 29k, am29005, am29030, am29035, am29040, am29050, am29200, am29202, am29205, am29240, am29243, am29245, xray29k, minimon29k, and scalable clocking are trademarks of advanced micro devices, inc. high c is a registered trademark of metaware, inc. product names used in this publication are for identification purposes only and may be trade- marks of their respective companies. ? 1993 advanced micro devices, inc.

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